1. Field of the Invention
The present invention relate to a bi-directional bus circuitry and, more specifically, to a bi-directional bus circuitry used for a semiconductor device such as a microprocessor, capable of high speed and stable bi-directional data transmission.
2. Description of the Background Art
Along with the recent increase in scale of semiconductor devices such as an LSI and associated increase in chip size, bus lines for signal transmission within the semiconductor devices come to be longer. The longer bus line means increased parasitic resistance and parasitic capacitance, which present the problem of increased time of signal transmission over the bus lines.
When the direction of signal transmission over a bus line is limited in one direction, the speed of transmission may be improved in a relatively simple manner, by inserting a repeater circuit functioning as a signal buffer appropriately into the elongated bus line. If the signal transmission over the bus line is bi-directional, however, a repeater having a function enabling bi-directional signal amplification and a circuit block controlling direction of signal transmission in each repeater circuit (such circuit is also referred to as an arbiter circuit) are necessary.
FIG. 9 is a block diagram representing a configuration of a conventional bi-directional bus circuitry 500.
Referring to FIG. 9, bi-directional bus circuitry 500 transmits data to be input/output to and from four circuit blocks 10-a to 10-d, for example, over a data bus which is divided into bus nodes Nb1 and Nb2. The data to be transmitted on the data bus is a digital data having two signal levels, that is, a high level (hereinafter also denoted as H level) and a low level (hereinafter also denoted as L level).
Circuit blocks 10-a and 10-b are connected to bus node Nb-1, while circuit blocks 10-c and 10-d are connected to bus node Nb2. Circuit blocks 10-a to 10-d have input buffers 12-a to 12-d and output buffers 14-a to 14-d, respectively.
Bi-directional bus circuitry 500 includes a repeater circuit 50 connected between bus nodes Nb1 and Nb2. Repeater circuit 50 includes a tristate buffer 51 amplifying and transmitting a signal in a direction from bus node Nb1 to bus node Nb2, and a tristate buffer 52 amplifying and transmitting a signal in a direction from bus node Nb2 to bus node Nb1.
Tristate buffers 51 and 52 function as buffers and amplify signals, when corresponding repeater control signals CRP1 and CRP2 are active (H level), respectively. The tristate buffers are each set to a high-impedance state, when the corresponding repeater control signals are inactive (L level).
Bi-directional bus circuitry 500 further includes an arbiter circuit 520 designating a circuit block to/from which data is to be input/output and controlling direction of signal transmission of repeater circuit 50.
Arbiter circuit 520 includes a circuit block designating circuit 25 receiving circuit block information for specifying a circuit block as an object of data output and outputting circuit block designating signals CSBa to CSBd.
Arbiter circuit 520 has a logic gate LG50 providing as an output a result of an OR operation between circuit block designating signals CSBa and CSBb, and a logic gate LG52 providing as an output the result of an OR operation between circuit block designating signals CSBc and CSBd. Logic gates LG50 and LG52 generate repeater control signals CLP1 and CLP2, respectively.
Therefore, when data output is designated in either one of circuit blocks 10-a and 10-b connected to bus node Nb1, arbiter circuit 520 activates tristate buffer 51 and designates signal transmission from bus node Nb1 to bus node Nb2.
When data output is designated in either one of circuit blocks 10-c and 10-d connected to bus node Nb2, arbiter circuit 520 activates tristate buffer 52 and designates signal transmission from bus node Nb2 to bus node
In FIG. 9, control signals used for data input to each of the circuit blocks are not shown for simplicity of drawings.
Because of such a configuration, even when the bus line becomes long, the direction of signal transmission is controlled and the data to be transmitted is amplified by arbiter circuit 520 and repeater circuit 50, whereby data can be transmitted at high speed over the long data bus.
In the configuration shown in FIG. 9, however, when the data bus is unused, that is, when none of the circuit blocks 10-a to 10-d connected to the data bus uses the data bus, circuit block designating signals CSBa to CSBd are all set to the inactive state (L level), and accordingly, repeater control signals CRP1 and CRP2 are also inactivated (L level). Consequently, tristate buffers 14-a to 14-d in respective circuit blocks as well as tristate buffers 51 and 52 in the repeater circuit 50 are all set to the high impedance state, so that bus nodes Nb1 and Nb2 both come to have potential levels not fixed. Such a state is generally referred to as a floating state.
With the potential level of the bus node being unfixed, the potential level of the bus node comes to be the intermediate potential, possibly causing a constant current, which will be consumed wastefully, in the input and output buffers of the circuit blocks which are connected to the bus node.
If the potential of the bus node should be higher than a power supply potential, which corresponds to the H level potential of the data or lower than the ground potential which corresponds to the L level potential of the data because of a noise or the like, there is a possibility of circuit break down in the input and output buffers of the circuit blocks connected to the bus node.
Japanese Patent Laying-Open No. 63-85852 proposes a solution to this problem of unfixed potential level of the data bus, which solution provides a bus circuitry configuration allowing fixing of the bus potential when the bus is not used.
FIG. 10 is a schematic diagram of a conventional bus circuitry allowing fixing of the bus potential when not in use.
Referring to FIG. 10, bus circuitry 600 includes n (n: natural number) tristate buffers GT1 to GTn provided corresponding to data D1 to Dn, respectively; a bus line BUS connected to an output node of each tristate buffer; a transistor QN provided between bus line BUS and a ground node; and an NOR gate GC1 for controlling ON/OFF of transistor QN.
Tristate buffers GT1 to GTn transmit corresponding data D1 to Dn to bus line BUS, in response to corresponding control signals C1 to Cn, respectively. A tristate buffer, corresponding control signal of which is inactive, is set to the high-impedance state.
In bus circuitry 600, when all control signals C1 to Cn are inactive and bus line BUS is not used, the output of NOR gate GC1 is set to the H level. Therefore, when the transistor QN is turned on, bus line BUS is connected to the ground node (potential level: GND).
More specifically, in bus circuitry 600, even when all the tristate buffers for providing corresponding data are set to the high-impedance state and bus line BUS is not used, it is possible to fix the potential level of bus line BUS at a prescribed potential level, in this example at the ground potential. Therefore, problems resulting from the unfixed potential level of the bus line BUS can be avoided.
As will be described in detail later, however, it is difficult to apply the technique for fixing the bus potential when not in use shown in FIG. 10, directly to a bi-directional bus circuitry.